The present invention relates generally to MOSFET transistors and more generally to DMOS transistors having a trench structure.
DMOS (Double diffused MOS) transistors are a type of MOSFET (Metal On Semiconductor Field Effect Transistor) that use diffusion to form the transistor regions. DMOS transistors are typically employed as power transistors to provide high voltage circuits for power integrated circuit applications. DMOS transistors provide higher current per unit area when low forward voltage drops are required.
A typical discrete DMOS circuit includes two or more individual DMOS transistor cells which are fabricated in parallel. The individual DMOS transistor cells share a common drain contact (the substrate), while their sources are all shorted together with metal and their gates are shorted together by polysilicon. Thus, even though the discrete DMOS circuit is constructed from a matrix of smaller transistors, it behaves as if it were a single large transistor. For a discrete DMOS circuit it is desirable to maximize the conductivity per unit area when the transistor matrix is turned on by the gate.
One particular type of DMOS transistor is a so-called trench DMOS transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin oxide layer and filled with polysilicon, allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench DMOS transistors are disclosed in U.S. Pat. Nos. 5,072,266, 5,541,425, and 5,866,931.
The cell density in a conventional DMOS circuit is limited to about 100 M/in2. This density corresponds to a distance of about 2.0 microns between adjacent trenches. This limitation arises because the lateral dimension of the source regions of the DMOS transistors must be large enough to allow adequate diffusion of n-type carriers.
Accordingly, it would be desirable to provide a trench DMOS circuit in which the density of transistor cells is increased by reducing the lateral dimension of the source regions.
The present invention provides a trench DMOS transistor cell that includes a substrate of a first conductivity type and a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and a conductive electrode is placed in the trench overlying the insulating layer. A source region of the first conductivity type is located in the body region adjacent to the trench. The source region includes a first layer and a second layer disposed over the first layer. The first layer has a lower dopant concentration of the first conductivity type relative to the dopant concentration of the second layer.
In accordance with one aspect of the invention, at least a portion of the first layer of the source region extends to a depth below a surface level of the conductive electrode. In some cases substantially all of the first layer of the source region extends to a depth below a surface level of the conductive electrode. Moreover, in some of these cases substantially all of the first layer of the source region and substantially none of the second layer extends to a depth below a surface level of the conductive electrode.
In accordance with another aspect of the invention, the body region includes a contact region more heavily doped than an underlying portion of the body region. The contact region provides electrical contact to the underlying body region.
In accordance with yet another aspect of the invention, the first layer is doped with phosphorous and the second layer is doped with arsenic.
In accordance with one particular embodiment of the invention, the first layer is doped to a concentration between about 5xc3x971017 and 5xc3x971018 cmxe2x88x923 and the second layer is doped to a concentration between about 4xc3x97109 and 8.0xc3x971019.